【正】 Y2002-63121-626 0220594亚纳秒时域内插器和-50dBc 寄生电平的30MHz 直接数字同步时钟发生器=A 30MHz DDS clock generatorwith sub-ns time domain interpolator and -50dBc spuriouslevel[会,英]/Heiskanen,A.& Mantyniemi,A.//TheIEEE International Symposium on Circuits and SystemsVol.4 of 5.—626~629(HE)Y2002-63121-638 0220595可再次使用微处理机核心的基于微分精细调谐延迟的全数字时钟发生器恒定核心=An all-digital clock gen-erator firm-core based on differential fine-tuned delay forreusable microprocessor cores[会,英]/Olivieri.M.&