FPGA Design of an Intra 16 ×16 Module for H.264/AVC Video Encoder

• 作者: Ahmed Ben Atitallah Hassen Loukil Imen Werda Nouri Masmoudi Patrice Kadionik
• 来源期刊: 电路与系统(英文)
• 学科: 工学
• 关键词: NIOS H.264 FPGA INTRA 16 × 16 NIOS-II SOPC Design
• 年，卷（期）: dlyxtyw_2010,（1）
• 页码范围: 18-29
• 页数: 12页
• 分类号: TN91

摘要

In this paper, we propose novel hardware architecture for intra 16 × 16 module for the macroblock engine of a new video coding standard H.264. To reduce the cycle of intra prediction 16 × 16, transform/quantization, and inverse quantization/inverse transform of H.264, an advanced method for different operation is proposed. This architecture can process one macroblock in 208 cycles for all cases of macroblock type by processing 4 × 4 Hadamard transform and quantization during 16 × 16 prediction. This module was designed using VHDL Hardware Description Language (HDL) and works with a 160 MHz frequency using ALTERA NIOS-II development board with Stratix II EP2S60F1020C3 FPGA. The system also includes software running on an NIOS-II processor in order to implementing the pre-processing and the post-processing functions. Finally, the execution time of our HW solution is decreased by 26% when compared with the previous work.