Switchable PLL Frequency Synthesizer andHot Carrier Effects

• 作者: Ashok Srivastava Yang Liu Yao Xu
• 来源期刊: 电路与系统(英文)
• 学科: 工学
• 关键词: CMOS Phase-Locked LOOP Voltage-Controlled OSCILLATOR HOT CARRIER Effects JITTER Phase Noise
• 年，卷（期）: 2011,（1）
• 页码范围: 45-52
• 页数: 8页
• 分类号: TN7

摘要

In this paper, a new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed to increase its tuning range. The switchable PLL which integrates two phase-locked loops with different tuning frequencies are designed and fabricated in 0.5 μm n-well CMOS process. Cadence/Spectre simulations show that the frequency range of the switchable phased-locked loop is between 320 MHz to 1.15 GHz. The experimental results show that the RMS jitter of the phase-locked loop changes from 26 ps to 123 ps as output frequency varies. For 700 MHz carrier frequency, the phase noise of the phase-locked loop reaches as low as ?81 dBc/Hz at 10 kHz offset frequency and ?104 dBc/Hz at 1 MHz offset frequency. A device degradation model due to hot carrier effects has been used to analyze the jitter and phase noise performance in an open loop voltage-controlled oscillator. The oscillation frequency of the voltage-controlled oscillator decreases by approximately 100 to 200 MHz versus the bias voltage and the RMS jitter increases by 40 ps under different phase-locked loop output frequencies after 4 hours of stress time.