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摘要:
With the recent advances of the VLSI technologies, stabilizing the physical behavior of VLSI chips is becoming a very complicated problem. Power grid optimization is required to minimize the risks of timing error by IR drop, defects by electro migration (EM), and manufacturing cost by the chip size. This problem includes complicated tradeoff relationships. We propose a new approach by observing the direct objectives of manufacturing cost, and timing error risk caused by IR drop and EM. The manufacturing cost is based on yield for LSI chip. The optimization is executed in early phase of the physical design, and the purpose is to find the rough budget of decoupling capacitors that may cause block size increase. Rough budgeting of the power wire width is also determined simultaneously. The experimental result shows that our approach enables selection of a cost sensitive result or a performance sensitive result in early physical design phase.
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篇名 A Power Grid Optimization Algorithm by Direct Observation of Manufacturing Cost Reduction
来源期刊 电路与系统(英文) 学科 医学
关键词 Power Grid Optimization MANUFACTURING Cost TIMING VIOLATION DECOUPLING Capacitor
年,卷(期) dlyxtyw_2012,(4) 所属期刊栏目
研究方向 页码范围 325-333
页数 9页 分类号 R73
字数 语种
DOI
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研究主题发展历程
节点文献
Power
Grid
Optimization
MANUFACTURING
Cost
TIMING
VIOLATION
DECOUPLING
Capacitor
研究起点
研究来源
研究分支
研究去脉
引文网络交叉学科
相关学者/机构
期刊影响力
电路与系统(英文)
月刊
2153-1285
武汉市江夏区汤逊湖北路38号光谷总部空间
出版文献量(篇)
286
总下载数(次)
0
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