Chip design of a 5.8-GHz fractional-N frequency synthesizer with a tunable Gm-C loop filter

• 来源期刊: 中国物理B（英文版）
• 关键词: Gm-C loop filter phase-locked loop PLL voltage-controlled oscillator (VCO)
• 年，卷（期）: 2012,（8）
• 页码范围: 270-277
• 页数: 8页
• 语种: 英文
• DOI: 10.1088/1674-1056/21/8/084210

摘要

This paper proposes a novel Gm-C loop filter insteai of a conventional passive loop filter used in a phase-locked loop.The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced.Furthermore,the MASH 1-1-1 sigma-delta (Σ△) modulator is adopted for performing the fractional division number and hence improves the phase noise as well.Measured results show that the locked phase noise is -114.1 dBc/Hz with lower Gm-C bandwidth and -111.7 dBm/C with higher Gm-C bandwidth at 1 MHz offset from carrier of 5.68 GHz.Including pads and built-in Gm-C filter,the chip area of the proposed frequency synthesizer is 1.06 mm2.The output power is -8.69 dBm at 5.68 GHz and consumes 56 mW with an off-chip buffer from 1.8-V supply voltage.