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摘要:
In this paper, a cascade Sigma-Delta (ΣΔ) Analog to Digital Converter (ADC) for multistandard radio receiver was presented. This converter is supposed to be able to support GSM, UMTS, Wifi and WiMAX communication standards. The Sigma-Delta modulator makes use of 4 bit quantizer and Data-Weighted-Averaging (DWA) technique to attain high linearity over a wide bandwidth. A top-down design methodology was adopted to provide a reliable tool for the design of reconfigurable high-speed ΣΔMs. VHDL-AMS language was used to model the analog and mixed parts of the selected 2-1-1 cascade ΣΔ converter and to verify their reconfiguration parameters based on behavioural simulation. This multistandard architecture was high level sized to adapt the modulator performance to the different standards requirements. The effects of circuit non-idealities on the modulator performance were modeled and analyzed in VHDLAMS to extract the required circuit parameters.
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篇名 Behavioral Modeling and Simulation of Cascade Multibit ΣΔ Modulator for Multistandard Radio Receiver
来源期刊 电路与系统(英文) 学科 工学
关键词 ΔΣ ADC MULTISTANDARD VHDL-AMS Language BEHAVIOURAL Simulation
年,卷(期) dlyxtyw_2013,(1) 所属期刊栏目
研究方向 页码范围 67-74
页数 8页 分类号 TN7
字数 语种
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ΔΣ
ADC
MULTISTANDARD
VHDL-AMS
Language
BEHAVIOURAL
Simulation
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期刊影响力
电路与系统(英文)
月刊
2153-1285
武汉市江夏区汤逊湖北路38号光谷总部空间
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286
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