Timing-Driven Variation-Aware Partitioning and Optimization of Mixed Static-Dynamic CMOS Circuits

• 作者: Kumar Yelamarthi
• 来源期刊: 电路与系统(英文)
• 学科: 工学
• 关键词: TIMING Optimization Dynamic CMOS CIRCUITS Process VARIATIONS DELAY UNCERTAINTY
• 年，卷（期）: dlyxtyw,（2）
• 页码范围: 202-208
• 页数: 7页
• 分类号: TP39

摘要

The advancement in CMOS technology has surpassed the progress in computer aided design tools, creating an avenue for new design optimization flows. This paper presents a design level transistor sizing based timing optimization algorithms for mixed-static-dynamic CMOS logic designs. This optimization algorithm performs timing optimization through partitioning a design into static and dynamic circuits based on timing critical paths, and is further extended through a process variation aware circuit level timing optimization algorithm for dynamic CMOS circuits. Implemented on a 64-b adder and ISCAS benchmark circuits for mixed-static-dynamic CMOS, the design level optimization algorithm demonstrated a critical path delay improvement of over 52% in comparison with static CMOS implementation by state-of-the-art commercial optimization tools.