Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits

• 作者: Ahmed H. Madian Hassanein H. Amer Mohamed B. Abdelhalim Mohamed F. Abu-Elyazeed Omnia S. Ahmed
• 来源期刊: 电路与系统(英文)
• 学科: 医学
• 关键词: Dynamic Power ESTIMATION LOGIC PICTURES CMOS Digital LOGIC Circuits TOGGLE Rate Unit-Delay Model
• 年，卷（期）: dlyxtyw_2013,（3）
• 页码范围: 276-279
• 页数: 4页
• 分类号: R73

摘要

In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes’ toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlosimulation methods.