High-Throughput and Area-Efficient FPGA Implementations of Data Encryption Standard (DES)

• 作者: Eyad Taqieddin Khaldoon Mhaidat Raed Bani-Hani Salah Harb
• 来源期刊: 电路与系统(英文)
• 学科: 医学
• 关键词: DES FPGA PIPELINED ITERATIVE SECURITY Efficiency ENCRYPTION
• 年，卷（期）: dlyxtyw_2014,（3）
• 页码范围: 45-56
• 页数: 12页
• 分类号: R73

摘要

One of the most popular standards for protecting confidential information is the Data Encryption Standard (DES). Although it has been replaced by the Advanced Encryption Standard (AES), it is still widely used in Automatic Teller Machines (ATM’s), smartcards, and mobile phone SIM cards. In this paper, we present area-efficient and high-throughput FPGA implementations of the DES which are developed using the Xilinx FPGA ISE design suite. In fact, we propose modifications on the fastest DES design reported in the literature and achieve 1.1 times higher speed. Also, we introduce an 8-stage pipelined design that needs only 0.75 times the registers and consumes 0.65 times the power of a similar 16-stages pipelined design. High-speed design and synthesis optimization techniques including pipelining, register retiming, and logic replication are used. Post- layout synthesis results show that the proposed implementations achieve high throughput-to-area ratio. To make a fair comparison, the proposed designs were synthesized using matching FPGA devices as being used by other implementations reported in the literature.