A 1-GHz, 7-mW, 8-Bit Subranging ADC without Resistor Ladder Using Built-In Threshold Calibration

• 作者: Daiki Tabira Futoshi Shimozono Kenichi Ohhata Masataro Iwamoto Wataru Yoshimura
• 来源期刊: 电路与系统(英文)
• 学科: 工学
• 关键词: Analog-to-Digital Convertor Subranging Architecture RESISTOR LADDER Foreground CALIBRATION OFFSET DRIFT
• 年，卷（期）: 2014,（4）
• 页码范围: 76-88
• 页数: 13页
• 分类号: TN7

摘要

A subranging analog-to-digital converter (ADC) features high-speed and relatively low-power. The limiting factors of power reduction in subranging ADCs are the resistor ladder and the comparator. We propose an ADC architecture combining a capacitive digital-to-analog convertor and built-in threshold calibration to eliminate the resistor ladder, resulting in a low-power subranging ADC. We also propose a calibration technique comprising of metal-oxide-metal capacitor, MOS switch, and scaling capacitor to reduce the power consumption of the comparator and an offset drift compensation technique to enable precise foreground calibration. We designed an 8-bit, 1-GHz subranging ADC by applying these techniques, and post-layout simulation results demonstrated a power consumption of 7 mW and figure of merit of 51 fJ/conv.-step.