An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer

• 作者: 吕孟山 周坤 张彦辉 李鹏程 石先龙 罗小蓉 罗尹春
• 来源期刊: 中国物理B（英文版）
• 关键词: trench U-shaped gate specific on-resistance breakdown voltage
• 年，卷（期）: 2015,（4）
• 页码范围: 047304-1-047304-6
• 页数: 1页
• 语种: 英文
• DOI: 10.1088/1674-1056/24/4/047304

摘要

An ultra-low specific on-resistance (Ron,sp) oxide trench-type silicon-on-insulator (SOI) lateral double-diffusion metal–oxide semiconductor (LDMOS) with an enhanced breakdown voltage (BV ) is proposed and investigated by sim-ulation. There are two key features in the proposed device:one is a U-shaped gate around the oxide trench, which extends from source to drain (UG LDMOS);the other is an N pillar and P pillar located in the trench sidewall. In the on-state, elec-trons accumulate along the U-shaped gate, providing a continuous low resistance current path from source to drain. The Ron,sp is thus greatly reduced and almost independent of the drift region doping concentration. In the off-state, the N and P pillars not only enhance the electric field (E-field) strength of the trench oxide, but also improve the E-field distribution in the drift region, leading to a significant improvement in the BV . The BV of 662 V and Ron,sp of 12.4 m?·cm2 are achieved for the proposed UG LDMOS. The BV is increased by 88.6%and the Ron,sp is reduced by 96.4%, compared with those of the conventional trench LDMOS (CT LDMOS), realizing the state-of-the-art trade-off between BV and Ron,sp.