Novel substrate trigger SCR-LDMOS stacking structure for high-voltage ESD protection application

• 作者: 乔明 张波 马金荣
• 来源期刊: 中国物理B（英文版）
• 关键词: electrostatic discharge high holding voltage latch-up STSCR-LDMOS
• 年，卷（期）: 2015,（4）
• 页码范围: 047303-1-047303-5
• 页数: 1页
• 语种: 英文
• DOI: 10.1088/1674-1056/24/4/047303

摘要

A novel substrate trigger semiconductor control rectifier-laterally diffused metal–oxide semiconductor (STSCR-LDMOS) stacked structure is proposed and simulated using the transimission line pulser (TLP) multiple-pulse simulation method in a 0.35-μm, 60-V biploar-CMOS-DMOS (BCD) process without additional masks. On account of a very low holding voltage, it is susceptible to latch-up-like danger for the semiconductor control rectifier-laterally diffused metal–oxide semiconductor (SCR-LDMOS) in high-voltage electro-static discharge (ESD) protection applications. Although the conventional stacking structure has achieved strong latch-up immunity by increasing holding voltage, excessive high trigger voltage does not meet requirements for an ESD protection device. The holding voltage of the proposed stacked structure is proportional to the stacking number, whereas the trigger voltage remains nearly the same. A high holding voltage of 30.6 V and trigger voltage of 75.4 V are achieved.