A 500-MS/s, 2.0-mW, 8-Bit Subranging ADC with Time-Domain Quantizer

• 作者: Daiki Hayakawa Kaihei Hotta Kenichi Ohhata Kenji Sewaki Kento Imayanagida Naoto Yamaguchi Yuuki Sonoda
• 来源期刊: 电路与系统(英文)
• 学科: 工学
• 关键词: Time-Based ADC Flash ADC TDC VTC CMOS
• 年，卷（期）: dlyxtyw_2017,（1）
• 页码范围: 1-13
• 页数: 13页
• 分类号: TN7

摘要

This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fabricated using 65-nm digital CMOS technology. The test chip demonstrated a high sampling frequency of 500 MHz and a low-power dissipation of 2.0 mW, resulting in a low FOM of 32 fJ/conversion-step.