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摘要:
Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.
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文献信息
篇名 SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey
来源期刊 电路与系统(英文) 学科 医学
关键词 Body BIASING Gate LEAKAGE JUNCTION LEAKAGE Power GATING MULTI-THRESHOLD SRAM Cell SUB-THRESHOLD LEAKAGE
年,卷(期) 2017,(2) 所属期刊栏目
研究方向 页码范围 23-52
页数 30页 分类号 R73
字数 语种
DOI
五维指标
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研究主题发展历程
节点文献
Body
BIASING
Gate
LEAKAGE
JUNCTION
LEAKAGE
Power
GATING
MULTI-THRESHOLD
SRAM
Cell
SUB-THRESHOLD
LEAKAGE
研究起点
研究来源
研究分支
研究去脉
引文网络交叉学科
相关学者/机构
期刊影响力
电路与系统(英文)
月刊
2153-1285
武汉市江夏区汤逊湖北路38号光谷总部空间
出版文献量(篇)
286
总下载数(次)
0
总被引数(次)
0
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