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With the introduction of EUV lithography,the photolithographic process in 5 nm logic process can be simplified to use mostly single exposure method.In a typical 5 nm logic process,the contact-poly pitch(CPP)is 44-50 nm,the minimum metal pitch(MPP)is around 30-32 nm.And the overlay budget is estimated to be 2.5 nm(on product overlay).Although the optical resolution of a 0.33NA exposure tool(such as ASML NXE3400)can reach below 32 nm pitch,stochastics in the EUV absorption in photoresists has limited its application to smaller pitches.For the CPP mentioned above,one can use 193 nm immersion lithography with Self-Aligned Double Patterning(SADP)technique to provide good image contrast(or CDU,LWR)as well as good overlay,as for the 10 and 7 nm generations.In the BEOL,however,the 30-32 pitch cannot be realized by a single EUV exposure with enough printing defect process window.If this pitch is to be done by 193 nm immersion lithography,more than 6-8 exposures are needed with very complicated overlay result.For EUV,this can be done through self-aligned LELE with both good CD and overlay control.We have done an optimization of the photolithographic process parameters for the typical metal with a self-developed aerial image simulator based on rigorous coupled wave analysis(RCWA)algorithm and the Abbe imaging routine with an EUV absorption model which describes stochastics.We have calibrated our model with wafer exposure data from several photoresists under collaboration with IMEC.As we have presented last year,to accommodate all pitches under a logic design rule,as well as to provide enough CDU for the logic device performance,in DUV lithography,a typical minimum exposure latitude(EL)for the poly and metal layers can be set at,respectively,18%and 13%.In EUV,due to the existence of stochastics,13%EL,which corresponds to an imaging contrast of 40%,seems not enough for the metal trenches,and to obtain an imaging contrast close to 100%,which yields an EL of 31.4%means that we need to relax minimum pitch to above 41 nm(conventi
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篇名 A Photolithography Process Design for 5 nm Logic Process Flow
来源期刊 微电子制造学报 学科 工学
关键词 5 NM LOGIC Process EUV SADP SELF-ALIGNED LELE RCWA stochastics MASK 3D SCATTERING
年,卷(期) 2019,(4) 所属期刊栏目
研究方向 页码范围 45-55
页数 11页 分类号 TN3
字数 语种
DOI
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研究主题发展历程
节点文献
5
NM
LOGIC
Process
EUV
SADP
SELF-ALIGNED
LELE
RCWA
stochastics
MASK
3D
SCATTERING
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研究来源
研究分支
研究去脉
引文网络交叉学科
相关学者/机构
期刊影响力
微电子制造学报
季刊
2578-3769
北京市北土城西路3号中科院微电子研究所
出版文献量(篇)
47
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0
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