A Low-Area, Low-Power Dynamically Reconfigurable 64-Bit Media Signal Processing Adder

• 作者: Priscilla Sharon Allwin Chien-In Henry Chen
• 来源期刊: 电脑和通信(英文)
• 学科: 工学
• 关键词: Media Signal Processing (MSP) Reconfigurable Adder Dynamic Reconfiguration
• 年，卷（期）: dnhtxyw_2021,（3）
• 页码范围: 54-69
• 页数: 16页
• 分类号: TP3

摘要

Multimedia devices like cellphones, radios, televisions, and computers require low-area and energy-efficient dynamically reconfigurable data paths to process the greedy computation algorithms for real-time audio/video signal<span> and image processing. In this paper, a novel low-area, energy-efficient 64-bit dynamically reconfigurable adder is presented. This adder can be run-time configured to different reconfigurable word lengths based on the partition signal commands provided. Moreover, the design is partitioned into sub-blocks based on functionality to save power, </span><i><span>i.e.</span></i><span>, configuring the computation only for the necessary data path, thus avoiding the unnecessary switching power from the data path computed values that do not get used. Only functions that are needed are powered on, and the rest of the functionality is powered off. The proposed 64-bit dynamically reconfigurable media signal processing (MSP) adder is implemented in the 180 nm CMOS technology at 1.8 V, requiring an area of 39,478 μm</span>^{<span style="vertical-align:super;">2</span>}<span> and a power of 79.24 mW. The dynamic MSP adder achieves a 15.7% reduction in area and a 59.2% reduction in power than the 64-bit MSP adder.</span>