Efficient Scheduling Mapping Algorithm for Row Parallel Coarse-Grained Reconfigurable Architecture

• 作者: Naijin Chen Zhen Wang Ruixiang He Jianhui Jiang Fei Cheng Chenghao Han
• 来源期刊: 清华大学学报自然科学版（英文版）
• 年，卷（期）: 2021,（5）
• 所属期刊栏目: REGULAR ARTICLES
• 页码范围: 724-735
• 页数: 12页
• 语种: 英文
• DOI: 10.26599/TST.2020.9010035

摘要

Row Parallel Coarse-Grained Reconfigurable Architecture(RPCGRA)has the advantages of maximum parallelism and programmable flexibility.Designing an efficient algorithm to map the diverse applications onto RPCGRA is difficult due to a number of RPCGRA hardware constraints.To solve this problem,the nodes of the data flow graph must be partitioned and scheduled onto the RPCGRA.In this paper,we present a Depth-First Greedy Mapping(DFGM)algorithm that simultaneously considers the communication costs and the use times of the Reconfigurable Cell Array(RCA).Compared with level breadth mapping,the performance of DFGM is better.The percentage of maximum improvement in the use times of RCA is 33％ and the percentage of maximum improvement in non-original input and output times is 64.4％(Given Discrete Cosine Transfor 8(DCT8),and the area of reconfigurable processing unit is 56).Compared with level-based depth mapping,DFGM also obtains the lowest averages of use times of RCA,non-original input and output times,and the reconfigurable time.