An integrated front-end vertical hall magnetic sensor fabricated in 0.18 μm low-voltage CMOS technology

• 作者: Zhengwu Shu Lei Jiang Xingxing Hu Yue Xu
• 来源期刊: 半导体学报（英文版）
• 年，卷（期）: 2022,（3）
• 所属期刊栏目: ARTICLES
• 页码范围: 59-66
• 页数: 8页
• 语种: 英文
• DOI: 10.1088/1674-4926/43/3/032402

摘要

An integrated front-end vertical CMOS Hall magnetic sensor is proposed for the in-plane magnetic field measure-ment.To improve the magnetic sensitivity and to obtain low offset,a fully symmetric vertical Hall device(FSVHD)has been op-timized with a minimum size design.A new four-phase spinning current modulation associated with a correlated double sampling(CDS)demodulation technique has been further applied to compensate for the offset and also to provide a linear Hall output voltage.The vertical Hall sensor chip has been manufactured in a 0.18 μm low-voltage CMOS technology and it occu-pies an area of 1.54 mm2.The experimental results show in the magnetic field range from-200 to 200 mT,the entire vertical Hall sensor performs with the linearity of 99.9％and the system magnetic sensitivity of 1.22 V/T and the residual offset of 60 μT.Meanwhile,it consumes 4.5 mW at a 3.3 V supply voltage.The proposed vertical Hall sensor is very suitable for the low-cost sys-tem-on-chip(SOC)implementation of 2D or 3D magnetic microsystems.