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摘要:
A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.
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篇名 A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering
来源期刊 通讯、网络与系统学国际期刊(英文) 学科 工学
关键词 VITERBI DECODER Convolutional Codes High-Speed Low Power Consumption Parallel Processing DEEP PIPELINING
年,卷(期) 2009,(6) 所属期刊栏目
研究方向 页码范围 575-582
页数 8页 分类号 TN7
字数 语种
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VITERBI
DECODER
Convolutional
Codes
High-Speed
Low
Power
Consumption
Parallel
Processing
DEEP
PIPELINING
研究起点
研究来源
研究分支
研究去脉
引文网络交叉学科
相关学者/机构
期刊影响力
通讯、网络与系统学国际期刊(英文)
月刊
1913-3715
武汉市江夏区汤逊湖北路38号光谷总部空间
出版文献量(篇)
763
总下载数(次)
1
总被引数(次)
0
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