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j-lanes hashing is a tree mode that splits an input message to j slices, computes j independent digests of each slice, and outputs the hash value of their concatenation. We demonstrate the performance advantage of j-lanes hashing on SIMD architectures, by coding a 4-lanes-SHA-256 implementation and measuring its performance on the latest 3rd Generation IntelR CoreTM. For messages whose lengths range from 2 KB to 132 KB, we show that the 4-lanes SHA-256 is between 1.5 to 1.97 times faster than the fastest publicly available implementation that we are aware of, and between ~2 to ~2.5 times faster than the OpenSSL 1.0.1c implementation. For long messages, there is no significant performance difference between different choices of j. We show that the 4-lanes SHA-256 is faster than the two SHA3 finalists (BLAKE and Keccak) that have a published tree mode implementation. Finally, we explain why j-lanes hashing will be faster on the coming AVX2 architecture that facilitates using 256 bits registers. These results suggest that standardizing a tree mode for hash functions (SHA-256 in particular) could be useful for performance hungry applications.
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篇名 A <i>j</i>-Lanes Tree Hashing Mode and <i>j</i>-Lanes SHA-256
来源期刊 信息安全(英文) 学科 医学
关键词 TREE MODE HASHING SHA-256 SHA3 Competition SIMD Architecture Advanced Vector Extensions Architectures AVX AVX2
年,卷(期) xxaqyw_2013,(1) 所属期刊栏目
研究方向 页码范围 7-11
页数 5页 分类号 R73
字数 语种
DOI
五维指标
传播情况
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研究主题发展历程
节点文献
TREE
MODE
HASHING
SHA-256
SHA3
Competition
SIMD
Architecture
Advanced
Vector
Extensions
Architectures
AVX
AVX2
研究起点
研究来源
研究分支
研究去脉
引文网络交叉学科
相关学者/机构
期刊影响力
信息安全(英文)
季刊
2153-1234
武汉市江夏区汤逊湖北路38号光谷总部空间
出版文献量(篇)
230
总下载数(次)
0
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