A Static Phase Offset Reduction Technique for Multiplying Delay-Locked Loop

• 作者: Tadeusz Kwasniewski Xinjie Wang
• 来源期刊: 电路与系统(英文)
• 学科: 医学
• 关键词: STATIC Phase OFFSET Multiplying Delay-Locked Loop DETERMINISTIC JITTER Reference SPUR PLL
• 年，卷（期）: dlyxtyw_2015,（1）
• 页码范围: 13-19
• 页数: 7页
• 分类号: R73

摘要

Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for MDLLs. The technique is based on the observation that the SPO of MDLL is mainly caused by the non-idealities on charge pump (e.g. sink and source current mismatch), and control line (e.g. gate leakage of loop filter and voltage controlled delay line (VCDL) control circuit). With a high gain stage inserting between phase detector/phase frequency detector (PD/PFD) and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The effectiveness of the proposed technique is validated by a Simulink model of MDLL. The equivalent SPO is measured by the power level of reference spur.