Test Vector Optimization Using Pocofan-Poframe Partitionin

• 作者: G.Maria Kalavathy P.PattunnaRajam Reeba korah
• 来源期刊: 计算机、材料和连续体(英文)
• 学科: 工学
• 关键词: PSEUDO EXHAUSTIVE TESTING POCOFAN (Primary Output Cone FanoutPartitioning) POFRAME partitioning combinational digital VLSI circuit TESTING criticalpath delay TESTING time design for TESTABILITY
• 年，卷（期）: 2018,（3）
• 页码范围: 251-268
• 页数: 18页
• 分类号: TN4

摘要

This paper presents an automated POCOFAN-POFRAME algorithm thatpartitions large combinational digital VLSI circuits for pseudo exhaustive testing. In thispaper, a simulation framework and partitioning technique are presented to guide VLSIcircuits to work under with fewer test vectors in order to reduce testing time and todevelop VLSI circuit designs. This framework utilizes two methods of partitioningPrimary Output Cone Fanout Partitioning (POCOFAN) and POFRAME partitioning todetermine number of test vectors in the circuit. The key role of partitioning is to identifyreconvergent fanout branch pairs and the optimal value of primary input node N andfanout F partitioning using I-PIFAN algorithm. The number of reconvergent fanout andits locations are critical for testing of VLSI circuits and design for testability. Hence, theirselection is crucial in order to optimize system performance and reliability. In the presentwork, the design constraints of the partitioned circuit considered for optimizationincludes critical path delay and test time. POCOFAN-POFRAME algorithm uses theparameters with optimal values of circuits maximum primary input cone size (N) andminimum fan-out value (F) to determine the number of test vectors, number of partitionsand its locations. The ISCAS’85 benchmark circuits have been successfully partitioned,the test results of C499 shows 45% reduction in the test vectors and the experimentalresults are compared with other partitioning methods, our algorithm makes fewer testvectors.