Design of a 1200-V Thin-Silicon-Layer p-Channel SOI LDMOS Device

• 作者: 吴丽娟 张波 张玲 李肇基 罗小蓉 胡盛东
• 来源期刊: 中国物理快报（英文版）
• 年，卷（期）: 2011,（12）
• 页码范围: 300-302
• 页数: 3页
• 语种: 英文
• DOI: 10.1088/0256-307X/28/12/128503

摘要

A 1200-V thin-silicon-layer p-channel silicon-on-insulator(SOI)lateral double-diffused metal-oxide-semiconductor (LDMOS)transistor is designed.The device named INI SO1 p-LDMOS is characterized by a series of equidistant high concentration n+ islands inserted at the interface of a top silicon layer and a buried oxide layer.Accumulation-mode holes,caused by the electric potential dispersion between the device surface and the substrate,are located in the spacing between two neighboring n+ islands,and greatly enhance the electric field of the buried oxide layer and therefore,effectively increase the device breakdown voltage.Based on a 2-μm-thick buried oxide layer and a 1.5-μm-thick top silicon layer,a breakdown voltage of 1224 V is obtained,resulting in the high electric field(608 V/μm)of the buried oxide layer.