Design of Low Power and High Speed CMOS Comparator for A/D Converter Application

• 作者: Radheshyam Gamad Shubhara Yewale
• 来源期刊: 无线工程与技术(英文)
• 学科: 工学
• 关键词: CMOS Comparato Low Power High Speed SIGMA-DELTA ADC and CADENCE
• 年，卷（期）: 2012,（2）
• 页码范围: 90-95
• 页数: 6页
• 分类号: TN7

摘要

This paper presents an improved method for design of CMOS comparator based on a preamplifier-latch circuit driven by a clock. Design is intended to be implemented in Sigma-delta Analog-to-Digital Converter (ADC). The main advantage of this design is capable to reduce power dissipation and increase speed of an ADC. The design is simulated in 0.18 μm CMOS Technology with Cadence environment. Proposed design exhibits good accuracy and a low power consumption about 102 μW with operating sampling frequency 125 MHz and 1.8 V supply. Simulation results are reported and compared with earlier work done and improvements are observed in this work.