Charge trapping memory device based on the Ga2O3 films as trapping and blocking layer

• 来源期刊: 中国物理B（英文版）
• 关键词: charge trapping memory SiO2 tunneling layer annealing temperature
• 年，卷（期）: 2019,（10）
• 页码范围: 112-116
• 页数: 5页
• 语种: 英文
• DOI: 10.1088/1674-1056/ab3e62

摘要

We present a new charge trapping memory (CTM) device with the Au/Ga2O3/SiO2/Si structure,which is fabricated by using the magnetron sputtering,high-temperature annealing,and vacuum evaporation techniques.Transmission electron microscopy diagrams show that the thickness of the SiO2 tunneling layer can be controlled by the annealing temperature.When the devices are annealed at 760 ℃,the measured C-V hysteresis curves exhibit a maximum 6 V memory window under a ±13 V sweeping voltage.In addition,a slight degradation of the device voltage and capacitance indicates the robust retention properties of flat-band voltage and high/low state capacitance.These distinctive advantages are attributed to oxygen vacancies and inter-diffusion layers,which play a critical role in the charge trapping process.