Methodology of Efficient Energy Design for Noisy Deep Submicron VLSI Chips

• 作者: WANGJun
• 来源期刊: 电子学报(英文版)
• 学科: 工学
• 关键词: VLSI 能量损耗 CMOS 集成电路 动态电路 电路噪声
• 年，卷（期）: 2004,（3）
• 页码范围: 522-525
• 页数: 4页
• 分类号: TN402
• 语种: 中文

摘要

Power dissipation is becoming increasingly important as technology continues to scale. This paper describes a way to consider the dynamic, static and shortcircuit power dissipation simultaneously for making complete, quantitative prediction on the total power dissipation of noisy VLSI chip. Especially, this new method elucidates the mechanism of power dissipation caused by the intrinsic noise of deep submicron VLSI chip. To capture the noise dependency of efficient energy design strategies for VLSI chip, the simulation of two illustrative cases are observed. Finally, the future works are proposed for the optimum tradeoff among the power, speed and area, which includes the use of floating-body partially depleted silicon-on-insulator CMOS technology.