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摘要:
This paper presents an efficient indirect fractional frequency synthesizer architecture based on the time delay digital tanlock loop. The indirect type frequency synthesis systems incorporate a low complexity high performance adaptation mechanism that enables them to remain in a locked state following the division process. The performance of the proposed fractional-N synthesizer under various input conditions is demonstrated. This includes sudden changes in the system input frequency as well as the injection of noise. The results of the extensive set of tests indicate that the fractional-N synthesizer, proposed in this work, performs well and is capable of achieving frequency divisions with fine resolution. The indirect frequency synthesizer also has a wide locking range and fast switching response. This is reflected by the system ability to regain its lock in response to relatively large variations in the input frequency within a few samples. The overall system performance shows high resilience to noise as reflected by the mean square error results.
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篇名 Fast Switching Fractional-N Frequency Synthesizer Architecture Using TDTL
来源期刊 通讯、网络与系统学国际期刊(英文) 学科 医学
关键词 FRACTIONAL SYNTHESIZER Time DELAY Tanlock LOOP REGISTER ADAPTATION
年,卷(期) 2009,(9) 所属期刊栏目
研究方向 页码范围 879-887
页数 9页 分类号 R73
字数 语种
DOI
五维指标
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研究主题发展历程
节点文献
FRACTIONAL
SYNTHESIZER
Time
DELAY
Tanlock
LOOP
REGISTER
ADAPTATION
研究起点
研究来源
研究分支
研究去脉
引文网络交叉学科
相关学者/机构
期刊影响力
通讯、网络与系统学国际期刊(英文)
月刊
1913-3715
武汉市江夏区汤逊湖北路38号光谷总部空间
出版文献量(篇)
763
总下载数(次)
1
总被引数(次)
0
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