基本信息来源于合作网站,原文需代理用户跳转至来源网站获取       
摘要:
The digital processing signal is one of the subdivisions of the analog digital converter interface;data transfer rate in modern telecommunications is a critical parameter. The greatest feature of parallel conversion rate (4-bit parallel Flash 5/s converter) is designed and modeled in 0.18 micron CMOS technology. Low speed swing operation as analog and digital circuits leads to high speed of low power operation power with 70 mVt 1.8 V A/D converter from the power dissipated during operation in the 5 GHz range. Average offset is used to minimize the effect of the bias of a comparator. This paper contains the 8-bit encoder of the metrical term code to direct binary code decreasing power consumption, which is shown by results and comparison with other designs using computer simulation. The results of the flash ADC time-interleaved are a more significant improvement in terms of power and areas than those previously reported.
内容分析
关键词云
关键词热度
相关文献总数  
(/次)
(/年)
文献信息
篇名 Design and Implementation of Double Base Integer Encoder of Term Metrical to Direct Binary
来源期刊 信号与信息处理(英文) 学科 医学
关键词 ADC CMOS VLSI High Speed Data CONVERTERS Code
年,卷(期) 2013,(4) 所属期刊栏目
研究方向 页码范围 370-374
页数 5页 分类号 R73
字数 语种
DOI
五维指标
传播情况
(/次)
(/年)
引文网络
引文网络
二级参考文献  (0)
共引文献  (0)
参考文献  (0)
节点文献
引证文献  (0)
同被引文献  (0)
二级引证文献  (0)
2013(0)
  • 参考文献(0)
  • 二级参考文献(0)
  • 引证文献(0)
  • 二级引证文献(0)
研究主题发展历程
节点文献
ADC
CMOS
VLSI
High
Speed
Data
CONVERTERS
Code
研究起点
研究来源
研究分支
研究去脉
引文网络交叉学科
相关学者/机构
期刊影响力
信号与信息处理(英文)
季刊
2159-4465
武汉市江夏区汤逊湖北路38号光谷总部空间
出版文献量(篇)
301
总下载数(次)
0
总被引数(次)
0
论文1v1指导