Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution

• 作者: Chin-Hsin Lin Marek Syrzycki
• 来源期刊: 电路与系统(英文)
• 学科: 工学
• 关键词: Vernier Time-to-Digital CONVERTER Dynamic-Logic PHASE FREQUENCY DETECTOR
• 年，卷（期）: 2011,（4）
• 页码范围: 365-371
• 页数: 7页
• 分类号: TN91

摘要

This paperpresents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of this phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution. The single-stage VTDC has been designed in 0.13μm CMOS technology. The simulation results demonstrate a linear input-output characteristic for input dynamic range from 0 to 1.6ns with a time resolution of 25ps.