Fast Signed-Digit Multi-operand Decimal Adders

• 作者: Erdal Oruklu Jafar Saniie Jeff Rebacz
• 来源期刊: 电路与系统(英文)
• 学科: 工学
• 关键词: Computer ARITHMETIC Decimal ARITHMETIC Signed-Digit Multi-operand ADDER BCD
• 年，卷（期）: 2011,（3）
• 页码范围: 225-236
• 页数: 12页
• 分类号: TP39

摘要

Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 754-2008, which standardized decimal floating-point. This paper presents a new architecture for two operand and multi-operand signed-digit decimal addition. Signed-digit architectures are advantageous because there are no carry-propagate chains. The proposed signed-digit adder reduces the critical path delay by parallelizing the correction stage inherent to decimal addition. For performance evaluation, we synthesize and compare multiple unsigned and signed-digit multi-operand decimal adder architectures on 0.18μm CMOS VLSI technology. Synthesis results for 2, 4, 8, and 16 operands with 8 decimal digits provide critical data in determining each adder's performance and scalability.