Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies

• 作者: Ze He Shi-Wei Zhao Tian-Qi Liu Chang Cai Xiao-Yu Yan Shuai Gao Yu-Zhu Liu Jie Liu
• 来源期刊: 核技术（英文版）
• 年，卷（期）: 2021,（12）
• 所属期刊栏目: NUCLEAR ELECTRONICS AND INSTRUMENTATION
• 页码范围: 64-76
• 页数: 13页
• 语种: 英文

摘要

A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk com-plementary metal oxide semiconductor technology.The single event upset(SEU)cross sections of this memory are obtained via heavy ion irradiation with a linear energy transfer(LET)value ranging from 1.7 to 83.4 MeV/(mg/cm2).Experimental results show that the upset threshold(LETth)of a 4 KB block is approximately 6 MeV/(mg/cm2),which is much better than that of a standard unhardened SRAM with an identical technology node.A 1 KB block has a higher LETth of 25 MeV/(mg/cm2)owing to the use of the error detection and correction(EDAC)code.For a Ta ion irradiation test with the highest LET value(83.4 MeV/(mg/cm2)),the benefit of the EDAC code is reduced significantly because the multi-bit upset pro-portion in the SEU is increased remarkably.Compared with normal incident ions,the memory exhibits a higher SEU sensitivity in the tilt angle irradiation test.Moreover,the SEU cross section indicates a significant dependence on the data pattern.When comprehensively considering HSPICE simulation results and the sensitive area distri-butions of the DICE cell,it is shown that the data pattern dependence is primarily associated with the arrangement of sensitive transistor pairs in the layout.Finally,some sug-gestions are provided to further improve the radiation resistance of the memory.By implementing a particular design at the layout level,the SEU tolerance of the memory is improved significantly at a low area cost.Therefore,the designed 65 nm SRAM is suitable for electronic systems operating in serious radiation environments.