CMOS analog and mixed-signal phase-locked loops: An overview

• 作者: Zhao Zhang
• 来源期刊: 半导体学报（英文版）
• 年，卷（期）: 2020,（11）
• 所属期刊栏目: REVIEWS
• 页码范围: 15-32
• 页数: 18页
• 语种: 英文
• DOI: 10.1088/1674-4926/41/11/111402

摘要

CMOS analog and mixed-signal phase-locked loops (PLL) are widely used in varies of the system-on-chips (SoC) as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including: 1) a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2) a summary of the design issues of the basic CPPLL architecture;3) a systematic introduction of the techniques for the performance enhancement of the CPPLL;4) a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter (＜ 100 fs) with lower power consumption compared with the CPPLL,including the injection-locked PLL (ILPLL),subsampling (SSPLL) and sampling PLL (SPLL);5) a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.