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For three fundamental input-protection schemes suitable for high-frequency CMOS ICs, which utilize protection devices such as NMOS transistors, thyristors, and diodes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit model of input HBM test environments for CMOS chips equipped with input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the peak voltage developed in the later stage of discharge, which corresponds to the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain strength and weakness of each protection scheme as an input ESD protection circuit for high-frequency ICs, and suggest valuable guidelines relating design of the protection devices and circuits.
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篇名 A Comparison Study of Input ESD Protection Schemes Utilizing NMOS, Thyristor, and Diode Devices
来源期刊 通讯与网络(英文) 学科 医学
关键词 ESD protection HBM NMOS THYRISTOR DIODE MIXED-MODE
年,卷(期) 2010,(1) 所属期刊栏目
研究方向 页码范围 11-25
页数 15页 分类号 R73
字数 语种
DOI
五维指标
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研究主题发展历程
节点文献
ESD
protection
HBM
NMOS
THYRISTOR
DIODE
MIXED-MODE
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引文网络交叉学科
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期刊影响力
通讯与网络(英文)
季刊
1949-2421
武汉市江夏区汤逊湖北路38号光谷总部空间
出版文献量(篇)
427
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0
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