Design of GGNMOS ESD protection device for radiation-hardened 0.18μm CMOS process

• 作者: Jianwei Wu Zongguang Yu Genshen Hong Rubin Xie
• 来源期刊: 半导体学报（英文版）
• 年，卷（期）: 2020,（12）
• 所属期刊栏目: ARTICLES
• 页码范围: 52-59
• 页数: 8页
• 语种: 英文
• DOI: 10.1088/1674-4926/41/12/122403

摘要

In this paper,the ESD discharge capability of GGNMOS (gate grounded NMOS) device in the radiation-hardened 0.18μm bulk silicon CMOS process (Rad-Hard by Process:RHBP) is optimized by layout and ion implantation design.The effects of gate length,DCGS and ESD ion implantation of GGNMOS on discharge current density and lattice temperature are studied by TCAD and device simulation.The size of DCGS,multi finger number and single finger width of ESD verification structures are designed,and the discharge capacity and efficiency of GGNMOS devices in ESD are characterized by TLP test technology.Finally,the optimized GGNMOS is verified on the DSP circuit,and its ESD performance is over 3500 V in HBM mode.