A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance

• 作者: Jongwoon Yoon Kwangsoo Kim
• 来源期刊: 半导体学报（英文版）
• 年，卷（期）: 2021,（6）
• 所属期刊栏目: ARTICLES
• 页码范围: 59-67
• 页数: 9页
• 语种: 英文
• DOI: 10.1088/1674-4926/42/6/062803

摘要

A split gate MOSFET(SG-MOSFET)is widely known for reducing the reverse transfer capacitance(CRSS).In a 3.3 kV class,the SG-MOSFET does not provide reliable operation due to the high gate oxide electric field.In addition to the poor stat-ic performance,the SG-MOSFET has issues such as the punch through and drain-induced barrier lowering(DIBL)caused by the high gate oxide electric field.As such,a 3.3 kV 4H-SiC split gate MOSFET with a grounded central implant region(SG-CIMOS-FET)is proposed to resolve these issues and for achieving a superior trade-off between the static and switching performance.The SG-CIMOSFET has a significantly low on-resistance(RON)and maximum gate oxide field(EOX)due to the central implant re-gion.A grounded central implant region significantly reduces the CRSS and gate drain charge(QGD)by partially screening the gate-to-drain capacitive coupling.Compared to a planar MOSFET,the SG MOSFET,central implant MOSFET(CIMOSFET),the SG-CIMOSFET improve the RON×QGD by 83.7％,72.4％and 44.5％,respectively.The results show that the device features not only the smallest switching energy loss but also the fastest switching time.